Ort: Hörsaal im LfI (Schneiderberg 32, Hannover, Deutschland)
Zeit: Mittwoch, den 11.05.05 um 17:30 - 18:30 + anschließendes Beisammensein
According to Moore''s law, scaling of CMOS technology by a factor of 0.7 every three years made the ICs smaller and smaller in order to achieve higher integration densities and higher switching speed, as well as lower power consumption. Due to the smaller area of the chips the costs have been reduced drastically. This made possible the key appliances in our daily life like the PC, mobile communication, the Internet and many others.
Today, the 90nm CMOS technology node is close to production and 65nm in development, already. As described by the latest ITRS 03 roadmap [1] detail, many roadblocks seem to appear for further reduction of feature sizes in the future. Among them, the key challenges are lithography for high volume production, the transistors with worse performance at small gate lengths, dynamic and non-volatile memories at ever smaller cell sizes, the interconnects with increasing resistance and capacitance, power dissipation and increasing processing complexity and costs. Therefore, a slowdown of the evolution of semiconductor technology in the future could be expected if performance cannot be improved with the next generation.
Nevertheless, all of them are not basic physical limitations as often argued in the past, but degraded performance. In order to sustain the demands of the ITRS 03 down to the 22nm CMOS generation many problems have to be solved.
Fig. 1 ITRS 03 nodes, gate lengths and transistor currents for high performance (hp) and low power (lop).
A key enabler to further feature size reduction is lithography. However, the increasing gap between microelectronics minimum feature size and the exposure wavelength (the so-called sub-wavelength gap)has become a key challenge for the semiconductor industry, e.g. for the 65nm node the targeted wavelength 193nm for exposure is a factor of 3 larger than the produced feature size. In the last 3 to 5 years mask technology has become a key contribute to bridge the sub wavelength gap. In particular optical enhancement technologies like Phase Shift Masks (PSM) technologies and Optical Proximity Correction (OPC) methods have become widely used tools to improve optical imaging.
Scaling of the presently used bulk transistor will become very difficult below the 45nm node, because ever higher doping concentrations are needed in order to reduce short channel effects. This increases junction capacitance and the junction leakage and reduces the carrier mobility. Therefore, new device architectures are needed. Among the most promising developments are Silicon on Insulator with several nm thick Si layers and multi-gate devices.
A TEM cross section of an thin body SOI transistor with 25nm gate length and 25nm Si thickness on 100nm buried oxide is given in Fig.2
Fig. 2 TEM cross section of a 25nm gate SOI transistor with 25nm Si and raised source drain.
Further reduction of the channel length will need two or more gates for the control of the channel together with thin Si layers, instead of only a single gate.
Focussing on the devices, bulk CMOS may run into performance constraints at the 45nm CMOS generation and below. But probably thin film SOI can take over and will allow further downscaling. Finally, multi-gate transistors with low doped channels are considered to be the best nano devices with respect to Ioff , Ion, and switching speed. They can be further improved implementing high mobility channels with strained Si. Therefore, it seems very likely that scaling of Si CMOS will continue down to the 22nm node in the year 2016, according to ITRS roadmap. Regarding device performance, Si transistors can operate well below 10nm gate length. Therefore, it is predicted that Si-CMOS technology will continue to dominate also in the era of nanoelectronics. The presentation will provide an overview of the work needed to stay on the roadmap as well as highlights from Corporate Research of Infineon Technologies AG.
